The present invention relates, in general, to methods for implementing self-aligned transistors, and more particularly, to a method for implementing a MESFET having a self-aligned gate and accurately controlled gate to drain spacing.
Gallium Arsenide (GaAs) metal semiconductor field effect transistors (MESFETs) have been used in many applications by the industry. Previous methods for implementing these GaAs MESFETs resulted in transistors with lower breakdown voltages than the desired breakdown voltage for some applications, including the power output stage of radio frequency equipment. These previous MESFET implementations formed the source and drain areas using one mask procedure, and a separate mask procedure for actually forming the gate electrode. Using different mask steps to form the gate electrode, and the source and drain areas often produced transistors that had a misalignment between the gate and the source and drain areas. The misalignment created variations in the gate to drain spacing between transistors which resulted in breakdown voltage variations between transistors. One method to overcome the effect of the variations was to have a large gate to drain spacing so that the misalignment had a smaller effect on the overall gate to drain spacing. The increased gate to drain spacing increased the drain resistance which adversely affected the performance of the MESFET. The increased spacing also increased the die area required to implement the MESFET thereby increasing its manufacturing cost.
Accordingly, it would be desirable to have a method for implementing the gate electrode of a transistor that provides accurate control of the gate to drain spacing and results in transistors having high breakdown voltage, low drain resistance, and low cost.